1. Field of the Invention
The present invention relates to a method and system for accessing a memory, particularly but not exclusively for directly accessing code for a CPU during booting.
2. Discussion of the Related Art
FIG. 1 is a schematic block diagram of a computer system with a direct interface boot arrangement using NOR flash. An integrated circuit 2 has a CPU 4 which is connected via a memory controller 6 to a DRAM 8 for normal operation of the system. In addition, the CPU 4 is connected via a flash memory interface (FMI) 10 to a NOR flash memory 12. The NOR flash memory 12 holds boot code and operating system code which are used by the CPU for its boot procedure. As a NOR flash memory can be accessed randomly at reasonable speed, the CPU can boot itself directly via the FMI 10 by fetching instructions from the NOR flash memory 12. After booting, subsequent operations are carried out using the DRAM 8.
One of the advantages of providing NOR flash memory to hold boot code is that it is directly interfaceable with the CPU and can be randomly accessed. However, NOR flash memory suffers from disadvantages relative to NAND flash memory in a number of respects. It will be appreciated that the term NOR flash memory relates to a flash memory where the memory cell structure has a NOR structure, such that the memory cells are connected to the bit lines in parallel so that if any memory cell is turned on by the corresponding word line, the bit line goes low. As the logic function is similar to a NOR gate, this cell arrangement is referred to as NOR flash. NAND flash uses a number of transistors in series and the unit cell has a smaller cell area than for NOR flash. Moreover, the erasing and programming times for NAND flash are significantly shorter than for NOR flash. For example, the programming time for NOR flash is typically more than an order of magnitude greater than for NAND flash. Moreover, NAND flash is cheaper and, because of the smaller cell area, has a much higher density.
The disadvantage of using NAND flash to hold boot code is that it is not randomly accessible. NAND flash memory has no dedicated address lines. It is controlled using an indirect input/output like interface through which commands and addresses are sent via an 8-bit bus to an internal command and address register. The result is that entire pages (or page segments) are read out at once, with bytes in a page only being available in the sequence in which they are stored in the memory. One way of using NAND flash memory for booting is illustrated in FIG. 2. FIG. 2 shows a chip 22 with a CPU 24 and a small embedded ROM 26. The embedded ROM holds a reset vector and boot loader code. The operating system code is held in a NAND flash memory 28 connected to the chip 22. After the boot loader code has been executed by the CPU, the operating system code is downloaded from the NAND flash memory 28 into a DRAM 30 which is also connected to the chip 22. The download is of course on a page-by-page basis, due to the read restriction of the NAND flash memory. Once the operating system code has been downloaded from the NAND flash 28 into the DRAM 30, it can be executed by the CPU in the normal way. This “duplication” of the operating system code prior to execution is termed “code shadowing”.
It would be advantageous to be able to make use of the advantages of NAND flash for holding boot code without the need for code shadowing when the boot code is to be executed.